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tc51wkm516axgn65,70 2002-03-05 1/11 ? access times: tc51wkm516axgn 65 70 access time 65 ns 70 ns ce1 access time 65 ns 70 ns oe access time 25 ns 25 ns page access time 30 ns 30 ns ? package: p-tfbga48-6mm 7mm 0.75mm pitch (wei g ht: g t yp .) tentative toshiba mos digital integrated circuit silicon gate cmos 2,097,152-word by 16-bit cmos pseudo static ram description the tc51wkm516axgn is a 33,554,432-bit pseudo static random access memory(psram) organized as 2,097,152 words by 16 bits. using toshiba?s cmos technology and advanced circuit techniques, it provides high density, high speed and low power. the device uses dual power supplies(2.6 to 3.1 v for core and 1.7 to 2.2 v for output buffer). the device also features sram-like w/r timing whereby the device is controlled by ce1 , oe , and we on asynchronous. the device has the page access operation. page size is 8 words. the device also supports deep power-down mode, realizing low-power standby. features ? organized as 2,097,152 words by 16 bits ? dual power supplies(2.6 to 3.1 v for core and 1.7 to 2.2 v for output buffer) ? direct ttl compatibility for all inputs and outputs ? deep power-down mode: memory cell data invalid ? page operation mode: page read operation by 8 words ? logic compatible with sram r/w ( we ) pin ? standby current standby 70 a deep power-down standby 5 a pin assignment (top view) pin names 1 2 3 4 5 6 a lb oe a0 a1 a2 ce2 b i/o9 ub a3 a4 ce1 i/o1 c i/o10 i/o11 a5 a6 i/o2 i/o3 d v ss i/o12 a17 a7 i/o4 v dd e v ddq i/o13 nc a16 i/o5 v ss f i/o15 i/o14 a14 a15 i/o6 i/o7 g i/o16 a19 a12 a13 we i/o8 h a18 a8 a9 a10 a11 a20 (fbga48) a0 to a20 address inputs a0 to a2 page address inputs i/o1 to i/o16 data inputs/outputs ce1 chip enable input ce2 chip select input we write enable input oe output enable input lb , ub data byte control inputs v dd power supply for core v ddq power supply for output buffer gnd ground nc no connection
tc51wkm516axgn65,70 2002-03-05 2/11 block diagram operation mode mode ce1 ce2 oe we lb ub add i/o1 to i/o8 i/o9 to i/o16 power read(word) l h l h l l x d out d out i ddo read(lower byte) l h l h l h x d out high-z i ddo read(upper byte) l h l h h l x high-z d out i ddo write(word) l h x l l l x d in d in i ddo write(lower byte) l h x l l h x d in invalid i ddo write(upper byte) l h x l h l x invalid d in i ddo outputs disabled l h h h x x x high-z high-z i ddo standby h h x x x x x high-z high-z i dds deep power-down standby h l x x x x x high-z high-z i ddsd notes: l = low-level input(v il ), h = high-level input(v ih ), x = v ih or v il , high-z = high-impedance v dd gnd i/o1 ce i/o8 ce i/o9 i/o16 oe ub lb a0 a1 a2 a3 a4 a5 ce2 memory cell array 4,096 512 16 (33,554,432) control signal generator sense amp a6 data output buffer data output buffer data input buffer data input buffer ce a9 a10 a11 a12 a13 a14 a15 a16 a17 a18 a19 row address buffer column address decoder row address decoder column address buffer i/o2 i/o3 i/o5 i/o4 i/o6 i/o7 i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 a7 a8 refresh control refresh address counter we ce1 a20
tc51wkm516axgn65,70 2002-03-05 3/11 absolute maximum ratings (see note 1) symbol rating value unit v dd power supply voltage ? 1.0 to 3.6 v v ddq output buffer power supply voltage ? 1.0 to v dd + 0.5 (3.6 v max) ? v v in input voltage for address and control pins ? 1.0 to 3.6 ? v v i/o input/output voltage for i/o pins ? 1.0 to v ddq + 0.5 v t opr. operating temperature ? 25 to 85 c t strg. storage temperature ? 55 to 150 c t solder soldering temperature (10 s) 260 c p d power dissipation 0.6 w i out short circuit output current 50 ma dc recommended operating conditions (ta = = = = ? ? ? ? 25c to 85c) symbol parameter min typ. max unit v dd power supply voltage 2.6 2.75 3.1 v ddq output buffer power supply voltage 1.7 1.8 2.2 input high voltage for address and control pins 1.6 ? v dd + 0.3* v ih input high voltage for i/o pins 1.6 ? v ddq + 0.3* v il input low voltage ? 0.3* ? 0.4 v dh data retention supply voltage 2.6 ? 3.1 v * : v ih (max) v dd +1.0 v/ v ddq +1.0 v with 10 ns pulse width v il (min) -1.0 v with 10 ns pulse width dc characteristics (ta = = = = ? ? ? ? 25c to 85c, v dd = = = = 2.6 to 3.1 v, v ddq = = = = 1.7 to 2.2 v) (see note 3 to 4) symbol parameter test condition min typ. max unit i il input leakage current v in = 0 v to v dd ? 1.0 ? + 1.0 a i lo output leakage current output disable, v out = 0 v to v dd ? 1.0 ? + 1.0 a v oh output high voltage i oh = ? 100 a v ddq ? 0.2 ? ? v v ol output low voltage i ol = 100 a ? ? 0.2 v i ddo1 operating current ce1 = v il ce2 = v ih , i out = 0 ma t rc = min ? ? 40 ma i ddo2 page access operating current ce1 = v il , ce2 = v ih , page add. cycling, i out = 0 ma t pc = min ? ? 25 ma i dds standby current(mos) ce1 = v dd ? 0.2 v, ce2 = v dd ? 0.2 v ? ? 70 a i ddsd deep power-down standby current ce2 = 0.2 v ? ? 5 a capacitance (ta = = = = 25c, f = = = = 1 mhz) symbol parameter test condition max unit c in input capacitance v in = gnd 10 pf c out output capacitance v out = gnd 10 pf note: this parameter is sampled periodically and is not 100% tested.
tc51wkm516axgn65,70 2002-03-05 4/11 ac characteristics and operating conditions (ta = = = = ? ? ? ? 25c to 85c, v dd = = = = 2.6 to 3.1 v, v ddq = = = = 1.7 to 2.2 v) (see note 5 to 11) tc51wkm516axgn 65 70 symbol parameter min max min max unit t rc read cycle time 65 10000 70 10000 ns t acc address access time ? 65 ? 70 ns t co chip enable ( ce1 ) access time ? 65 ? 70 ns t oe output enable access time ? 25 ? 25 ns t ba data byte control access time ? 25 ? 25 ns t coe chip enable low to output active 10 ? 10 ? ns t oee output enable low to output active 0 ? 0 ? ns t be data byte control low to output active 0 ? 0 ? ns t od chip enable high to output high-z ? 20 ? 20 ns t odo output enable high to output high-z ? 20 ? 20 ns t bd data byte control high to output high-z ? 20 ? 20 ns t oh output data hold time 10 ? 10 ? ns t pm page mode time 65 10000 70 10000 ns t pc page mode cycle time 30 ? 30 ? ns t aa page mode address access time ? 30 ? 30 ns t aoh page mode output data hold time 10 ? 10 ? ns t wc write cycle time 65 10000 70 10000 ns t wp write pulse width 50 ? 50 ? ns t cw chip enable to end of write 60 ? 60 ? ns t bw data byte control to end of write 60 ? 60 ? ns t as address set-up time 0 ? 0 ? ns t wr write recovery time 0 ? 0 ? ns t odw we low to output high-z ? 20 ? 20 ns t oew we high to output active 0 ? 0 ? ns t ds data set-up time 30 ? 30 ? ns t dh data hold time 0 ? 0 ? ns t cs ce2 set-up time 0 ? 0 ? ns t ch ce2 hold time 300 ? 300 ? s t dpd ce2 pulse width 10 ? 10 ? ms t chc ce2 hold from ce1 0 ? 0 ? ns t chp ce2 hold from power on 30 ? 30 ? s ac test conditions parameter condition output load 30 pf + 1 ttl gate input pulse level v dd ? 0.2 v, 0.2 v timing measurements v dd 0.5 reference level v dd 0.5 t r , t f 5 ns
tc51wkm516axgn65,70 2002-03-05 5/11 timing diagrams read cycle page read cycle (8 words access) d out i/o1 to i/o16 address a0 to a20 oe t rc t acc t od t oh valid data out t oe t be t oee t bd hi-z hi-z t co ub , lb t odo t ba t coe indeterminate ce1 ce2 we fix-h t pm t pc t rc t aoh fix-h hi-z hi-z ub , lb t be address a0 to a2 we ce1 ce2 d out i/o1 to i/o16 address a3 to a20 t aa t aoh t aoh t pc t aa t oh t bd t od t odo t oee t ba t oe t coe t co t acc d out d out d out d out t pc t aa oe * maximum 8 words
tc51wkm516axgn65,70 2002-03-05 6/11 write cycle 1 ( controlled) (see note 8) write cycle 2 ( controlled) (see note 8) ce ub , lb t as t bw t wr valid data in t odw t wp t ds t dh t oew (see note 11) (see note 10) hi-z t cw t wc (see note 9) (see note 9) address a0 to a20 we ce1 ce2 d out i/o1 to i/o16 d in i/o1 to i/o16 t ch we t wc t wp t as t cw t wr valid data in t odw t ds t dh t coe hi-z hi-z ub , lb t bw t be (see note 9) address a0 to a20 we ce1 ce2 t ch d out i/o1 to i/o16 d in i/o1 to i/o16
tc51wkm516axgn65,70 2002-03-05 7/11 write cycle 3 ( , controlled) (see note 8) ub lb t wc t wp t as t bw t wr t odw t ds t dh t be hi-z hi-z ub , lb t cw t coe address a0 to a20 we ce1 ce2 t ch d out i/o1 to i/o16 valid data in (see note 9) d in i/o1 to i/o16 t cw
tc51wkm516axgn65,70 2002-03-05 8/11 deep power-down timing power-on timing provisions of address skew read if multiple invalid address cycles shorter than t rc min sustain over 10 s, as least one valid address cycle over t rc min must be needed during 10 s. write if multiple invalid address cycles shorter than t wc min sustain over 10 s, as least one valid address cycle over t wc min with t wp min must be needed during 10 s. ce2 t cs t dpd t ch ce1 v dd ce2 t chc t chp t ch v dd min ce1 we address t rc min over 10 s ce1 we address t wc min over 10 s ce1 t wp min
tc51wkm516axgn65,70 2002-03-05 9/11 notes: (1) stresses greater than listed under ?absolute maximum ratings? may cause permanent damage to the device. (2) all voltages are reference to gnd. (3) i ddo depends on the cycle time. (4) i ddo depends on output loading. specified values are defined with the output open condition. (5) ac measurements are assumed t r , t f = 5 ns. (6) parameters t od , t odo , t bd and t odw define the time at which the output goes the open condition and are not output voltage reference levels. (7) data cannot be retained at deep power-down stand-by mode. (8) if oe is high during the write cycle, the outputs will remain at high impedance. (9) during the output state of i/o signals, input signals of reverse polarity must not be applied. (10) if ce1 or lb / ub goes low coincident with or after we goes low, the outputs will remain at high impedance. (11) if ce1 or lb / ub goes high coincident with or before we goes high, the outputs will remain at high impedance.
tc51wkm516axgn65,70 2002-03-05 10/11 package dimensions ( 4.0 ) 8.0 0.4 a 0.4 0.8 ( 5.6 ) 1.7 sab 0.08 0.45 0.05 b 0.32 0.05 1.2 max 5.9 0.05 6.0 sa 0.20 0.15 4 4-c0.4 8.9 0.05 9.0 sb 0.20 1 2 3 4 5 6 abcdefgh 0.1 0.1 s s 1.0 s weight: g (typ)
tc51wkm516axgn65,70 2002-03-05 11/11 ? toshiba is continually working to improve the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within specified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ? handling guide for semiconductor devices, ? or ? toshiba semiconductor reliability handbook ? etc.. ? the toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ? unintended usage ? ). unintended usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at the customer ? s own risk. ? the products described in this document are subject to the foreign exchange and foreign trade laws. ? the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by toshiba corporation for any infringements of intellectual property or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any intellectual property or other rights of toshiba corporation or others. ? the information contained herein is subject to change without notice. 000707eba restrictions on product use

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